The storage capacity of flash memories can be increased by increasing the number of bits stored per memory cell. Nitride programmable read-only memory (NROM) cells are non-volatile memory cells that can store two bits per cell. FIG. 1 shows a sectional view through an NROM cell as known in the prior art. In a memory, the gate G of the cell will be connected to a wordline and the two source/drain regions S/D will be connected to bitlines. Below the gate G is the so-called ONO layer which consists of a nitride layer NL sandwiched between a top oxide layer TO and a bottom oxide layer BO. Electric charge can be stored in the nitride layer NL at a first location B1 and at a second location B2. The amount of charge stored in each location can be adjusted independently from the charge stored in the other location, so that it is possible to store two bits in a single cell.
The amount of electrical charge stored determines a threshold voltage value Vth, which is the voltage applied to the gate G that is required for a channel of electrons to exist underneath the ONO layer in the semiconductor substrate SB so that the memory cell conducts current. The threshold voltage Vth is increased when electrons are trapped on the nitride layer. A high threshold voltage Vth corresponds to a programmed state (“0”) in which the cell does not conduct current, while a low threshold voltage Vth corresponds to an erased state (“1”) in which the memory cell conducts current.
Programming the first bit involves applying voltages of, for example, 4.5 V to the source/drain S/D which is close to the first location B1, 0 V to the second source/drain S/D, and 9 V to the gate G so that hot electrons will tunnel from the channel of the cell into the nitride layer NL.
Erasing the first bit involves hot hole injection by applying, for example, a voltage of 8 V to the source/drain S/D close to the first location B1, floating the other source/drain S/D and applying a negative voltage to the gate G. As a consequence, electrons trapped on the nitride layer enter the semiconductor substrate SB via Fowler-Nordheim tunnelling. Ideally, the threshold voltage Vth thus reverts to the original, unprogrammed threshold voltage of the memory cell.
Reading the first bit involves applying a reading voltage VR that is between the threshold voltage of memory elements that have been erased and the threshold voltage of memory elements that have been programmed, i.e. a voltage that is between the high and the low threshold voltage, to the gate G and applying potentials of, for example, 0 V to the source/drain region S/D close to the first location B1 and 1.5 V to the other source/drain S/D region. By sensing the current flowing through the memory cell from one source/drain S/D to the other source/drain S/D, the state stored in the memory cell can be determined. For the same gate voltage the current flowing through an erased memory cell will be greater than that flowing through a programmed memory cell.
For reading, programming, and erasing the second bit, the voltages applied to the source/drain regions S/D near the first location B1 and the second location B2 are swapped.
The threshold voltages Vth of individual memory cells vary, inter alia, due to variations in the manufacture, the operating conditions and aging. FIG. 2 shows the threshold voltage distributions for memory cells storing an erased state (“1”) and a programmed (“0”) state. The horizontal axis represents the voltage that must be applied to the gate for the memory cell to conduct, that is the threshold voltage of the cells, while the vertical axis represents the number of memory cells N that conduct current at this voltage. In order to correctly read the states stored in the memory cells, the reading voltage VR applied to the gates G of the memory cells must lie between the lower reading voltage VL and the upper reading voltage VU. The lower reading voltage VL is the minimum voltage required for all the erased memory cells to conduct, the upper reading voltage VU is the maximum voltage allowed so that none of the programmed memory cells conduct. If the reading voltage VR is less than the lower reading voltage VL, then memory cells which are erased will be read as programmed, and if the reading voltage VR is greater than the upper reading voltage VU, then memory cells which are programmed will be read as erased. The voltage range between the upper reading voltage VU and the lower reading voltage VL forms the so-called “reading voltage window W”. If the reading voltage VR lies in this window, then the erased and programmed memory cells will be read correctly.
The threshold voltage Vth of memory cells changes with usage. During programming, electrons are trapped in the nitride layer NL near one of the locations B1 and B2 via hot-electron injection. During erasure, electrons are removed from the nitride layer. However, over numerous programming cycles, the distribution of the threshold voltages can shift so far that the reading voltage VR has to be adjusted in order to avoid reading failures of the memory. Besides the shift of the threshold voltages Vth, the distributions of the threshold voltages Vth of the erased and programmed memory cells increase in width with time so that the reading voltage window W shrinks with time. The difference between the upper reading voltage VU and the lower reading voltage VL may be as small as 100 mV. Once the distributions of the erased and programmed memory cells overlap, it is no longer possible to distinguish between programmed and erased cells.
In order to correctly read the data stored in the memory cells, the reading voltage VR must be adjusted to a suitable level. One method for determining a suitable reading voltage is the so-called “moving reference concept” in which the number of zeros read from a memory area at a certain reading voltage VR are compared to the number of zeros programmed into this memory area. The number of zeros programmed is calculated and stored in a so-called “zero counter” by the memory controller before the memory area is programmed. A high initial reading voltage VR is selected and reduced step by step until the number of zeros read from the memory area is equal to the number of zeros that were programmed into this memory area.
This concept is illustrated in FIG. 3A which shows the reading voltage window W and also shows how the reading voltage VR changes over time. Starting at an initial reading voltage Vi, the reading voltage VR is successively reduced by voltage steps S until the reading voltage VR falls within the reading voltage window W. Before each decrease, all the memory cells in the memory area are read and the number of zeros read is compared to the number of zeros that were programmed into this memory area. The threshold voltages Vth may shift between 1 to 1.5 V and the reading voltage window W may be as small as 100 mV so that twenty to thirty voltage steps of 50 mV are required to find a suitable reading voltage VR.
The moving reference concept has several disadvantages. Before each decrease in the reading voltage VR, all the memory cells in the memory area have to be read. This is relatively slow (several μs) as bitlines needed to address the memory cells have to be charged and discharged. If ten to twenty steps are needed for reading data with strongly shifted threshold voltage distributions, the response time is long and the reading performance of such a memory is poor. Additionally, repeatedly reading all the memory cells leads to an increase in power consumption, which is especially undesirable if the semiconductor memory is used in mobile devices.
One solution is to reduce the number of steps and to increase the step size. However, this leads to the problems illustrated in FIGS. 3B, 3C, 3D. If the initial reading voltage Vi is not high enough, that is, if it lies below the reading voltage window W, the algorithm fails, as shown in FIG. 3B. If the number of steps is limited and the step size S is small, it can happen that the reading voltage window W is lower than the last step, as illustrated in FIG. 3C. If the step size S is too large, i.e. larger than the reading voltage window W, it may also be impossible to find the right reading level, as shown in FIG. 3D. In each of these cases, “0” will be read as “1” if the reading voltage is too high and “1” will be read as “0” if the reading voltage is too low. This leads to wrong data and reading failures.